In the conventional programmable device, in a case where the utilization rate of internal elements is relatively high and a simultaneous operation rate with which the internal elements operate simultaneously is relatively high, noise may be generated in the internal power supply or ground. A threshold value of a clock buffer that is connected to a clock line within the programmable device may be affected by such noise and change, to thereby cause clock jitter. When the clock jitter is generated, a designed external AC characteristic may not be obtained. As a result, an appropriate signal transfer may not be possible between the programmable device and an external device or, a timing error may occur among registers of the internal circuit of the programmable device. When outputting data from the programmable device to the external device, there is an output timing to be satisfied in order to make the signal transfer while keeping the time required for the data to stabilize depending on changes in the data and the clock. Such an output timing may be achieved when the designed external AC characteristic is obtained.
Conventionally, when developing a platform, that is, an application of the programmable device, a noise reduction technique that embeds capacitors for noise reduction into the programmable device is employed by the design using CAD (Computer Aided Design). However, the noise anticipated by this noise reduction technique is for an average application. For this reason, if the capacitors for noise reduction, that may cope with all applications, were to be embedded in the programmable device, the capacitors would occupy a relatively large area within the programmable device, and the cost of the programmable device would increase. Hence, this noise reduction technique is not very practical. On the other hand, in SPICE (Simulation Program with Integrated Circuit Emphasis) that can compute the extent of the effect of the noise, the amount of capacitors required for noise reduction may be obtained from the amount of noise by carrying out a chip simulation for each application. However, this chip simulation requires an extremely long time and an extremely large number of hardware resources, and the cost of this chip simulation is extremely high. Hence, the technique that uses this chip simulation is also not very practical.
On the other hand, in order to operate the platform, that is, the application of the programmable device, it is necessary to increase the amount of capacitors for noise reduction required within the programmable device if an evaluation result of the actual programmable device indicates that the effect of the noise is relatively large. But in order to increase the amount of capacitors for noise reduction, it becomes necessary to re-develop the platform, and additional time and cost are required for the re-development or re-designing.
Therefore, when designing the programmable device, there are demands to use the platform of the existing programmable device, to avoid the increase in cost caused by the re-development, simulation and the like, and to suppress the clock jitter by specifying the location within the programmable device where the effect of the noise is relatively large or the effect of the noise may not be negligible.
Similar methods are disclosed in Japanese Laid-Open Patent Publications No. 7-131025, No. 1-206438, and No. 4-115634.
According to the conventional method of designing the semiconductor integrated circuit, such as the programmable device, there was a problem in that it is difficult to positively suppress the clock jitter in a relatively short time and at a relatively low cost.